1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which, although it does not incorporate a capacitor, can be used as a dynamic random access memory (DRAM) cell. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Recently, the semiconductor memory market has been prosperous. In connection with this, there has been a great deal of research advanced and conducted in the area of ultra large scale integration.
However, there are limits to which the realization of ultra large scale integration and large capacity can be accomplished using the current basic memory device structure. Accordingly, a new model of memory device is required.
In general, there are several memory devices having respective characteristics. For example, a DRAM memory device is not limited in its cycling, but is inferior in the density aspect because the unit cell of a DRAM is composed of one storage capacitor and one transistor. On the other hand, an electrically erasable programmable read only memory (EEPROM) device is composed of one stacked transistor. Through a thin tunnel oxide film, a floating gate is charged with electrons or the charged electrons are discharged from the floating gate, to thereby perform "programming" or "erasure" of the cell. Accordingly, the density of the EEPROM is good, but the cycling is limited to about 10.sup.7 possible programming/erasure occurrences. The DRAM and EEPROM will be described below with reference to the attached drawings.
FIG. 1 is a circuit diagram of a general DRAM cell. FIG. 2 is a cross-sectional view showing the structure of the general DRAM cell.
The conventional DRAM cell is constructed using one bit line (B/L), one word line (W/L), one access transistor (M1), one storage capacitor (Cs), and one sense amplifier (SA). Referring to this structure, a gate (G) of access transistor (M1) is connected to word line (W/L). A drain (D) of access transistor (M1) is connected to bit line (B/L). A source (S) of access transistor (M1) is connected to a first electrode of storage capacitor (Cs). A second electrode of storage capacitor (Cs) is connected to a polysilicon cell plate. Bit line (B/L) is connected to one input terminal of sense amplifier (SA). Another input terminal of sense amplifier (SA) is connected to a reference voltage (Vref).
The structure of the DRAM cell having the aforementioned circuit construction is shown in FIG. 2. That is, a P-type silicon substrate 1 is divided into a field region and an active region, and a field oxide film 2 is formed on the field region. A gate insulating film 3 and a gate electrode 4 are stacked sequentially on the active region of P-type silicon substrate 1. Source/drain regions (S,D), which are N-type impurity regions, are formed in the substrate 1 on both sides of gate electrode 4, thereby forming access transistor (M1).
Further, a first electrode 6 of the capacitor (Cs) is formed on source region (S) of access transistor (M1). A dielectric film 7 and a second electrode 8 are stacked on the surface of first electrode 6 of the capacitor (Cs). Moreover, bit line (B/L) is connected to drain region (D) of access transistor (M1). Reference numerals 5 and 9 designate insulating films.
The operation of the conventional DRAM cell constructed as described above will be explained below. First of all, it is assumed that, during an initial stage of the operation, P-type silicon substrate 1 is grounded and a voltage of Vcc (5V) is applied to second electrode 8 of the capacitor (Cs).
In this case, electrons are accumulated and an inversion layer formed in the surface of the P-type silicon region under second electrode 8. A depletion layer, in turn, is formed under the inversion layer.
Accordingly, in order to write a logic "1" in any one cell, 5V are applied to the bit line connected to drain (D) of access transistor (M1) of the above cell. At the same time, a voltage pulse of 5-6V is applied to the word line connected to gate (G) of access transistor (M1) of the above cell. If so, the access transistor is in an "on" state, so that the potential of the access transistor source of the above cell is raised to 5V.
At this time, the potential of the inversion layer formed in the surface of the P-type silicon region under second electrode 8 will be somewhat lower than 5V. This is because the voltage of 5V applied to second electrode 8 is decreased in some degree through the dielectric film of the storage capacitor located below second electrode 8.
Accordingly, the electrons accumulated in the inversion layer formed in the P-type silicon substrate surface under second electrode 8 flow into the source region of access transistor (M1), whose electron energy state is low. Thus, an empty potential well is formed in the surface of the P-type silicon region under second electrode 8. Such state shows a logic "1" in the binary system.
In order to write a logic "0" in any one cell, bit line (B/L) connected to the drain of the access transistor of the above cell is grounded. At the same time, a voltage pulse of 5-6V is applied to word line (W/L) connected to the gate of the access transistor of the above cell.
If so, the electrons flow from source region (S) of access transistor (M1) having a high electron energy to the empty potential well formed in the surface of the P-type silicon substrate, thereby filling the empty potential well. Accordingly, the electrons are accumulated in the inversion layer formed in the surface of the P-type silicon substrate under the capacitor. Such state shows a logic "0" in the binary system.
In order to read data from the above cell, bit line (B/L) is precharged to 0.5 Vcc (.about.2.5V), and then a voltage pulse of 5-6V is applied to the word line (W/L) of the above cell. If so, the electric charges charged in the storage capacitor (Cs) of the above cell flow to bit line (B/L), thereby changing the potential of bit line (B/L).
Since sense amplifier (SA) is a comparative circuit, if the potential of the bit line is higher than the reference voltage (.about.0.5 Vcc), a logic "1" is read. If the above potential is lower than the reference voltage, a logic "0" is read.
A displacement potential (.DELTA.V) of bit line (B/L) is expressed by the following equation (1): EQU .DELTA.V=.+-.0.5 Vcc (Cs)/(Cs+Cb) (1)
Here, Cs represents the static capacity of the storage capacitor (Cs), and Cb represents the static capacity of the bit line. Further, in equation (1), the (+) symbol corresponds to the case where a logic "1" is stored in the cell. The (-) symbol corresponds to the case where a logic "0" is stored in the cell.
The minimum voltage difference between the reference voltage and the bit line voltage, which can be distinguished by a sense amplifier, can be referred to as a "distinction ability" of the sense amplifier. The distinction ability of the sense amplifier in previous 1M DRAM devices is about 150-200 mV. Therefore, in the case where Vcc is 5V in equation (1), the ratio (r) of the bit line static capacity (Cb) and the storage capacitor static capacity (Cs), where (r=Cb/Cs), must be lower than 15 in order to make .DELTA.V higher than 150 mV. According to a previously published paper, in the case of a 1M DRAM device, Cs was 30-60 fF and Cb was 250-500 fF. Further, r was maintained at 7-15.
In such a general DRAM cell, integration is increased steadily, thereby reducing the size of the cell area. However, the distinction ability of the sense amplifier and the static capacity of the bit line cannot be decreased, as compared to the decrease in the size of the cell. Further, the static capacity of the storage capacitor is not decreased, as compared to the decrease in the size of the cell area.
Moreover, in order to prevent the "soft error" problem, which is among the most significant reliability problems confronted in DRAM technology, it is necessary to maintain the constant size of the static capacity of the storage capacitor. Due to this reason, the reduction of the static capacity of the storage capacitor is small, in spite of the steady increase of the DRAM integration and the reduction of the cell area size.
For example, in the case of a 256K DRAM, a design rule of about 2 mm has been used. In the case of a 256M DRAM, a design rule of about 0.25 .mu.m has been used. Accordingly, the cell area has been decreased by about 100 times.
However, if the static capacity of the storage capacitor is considered, such static capacity is about 40 fF in the 256K DRAM and about 25 fF in the 256M DRAM. Thus, the static capacity has been decreased by about 1.5 times.
In such a general DRAM, the static capacity of the storage capacitor must be maintained at almost the same size, in spite of the increase in integration. Therefore, there is a problem in that the integration has a limit.
Further, in order to form the storage capacitor while minimizing the cell area, a trench is formed in the substrate to thereby form the storage capacitor, or a stacked capacitor structure is used to form the storage capacitor. Thus, the semiconductor manufacturing process becomes complicated. In connection with this, there is a problem in that the semiconductor manufacturing process cost increases substantially.
FIG. 3 is a circuit diagram of a general flash EEPROM cell. FIG. 4 is a cross-sectional view showing the structure of the general flash EEPROM cell.
The general EEPROM cell is comprised of a floating gate avalanche injection metal oxide semiconductor (FAMOS) having a stacked gate transistor structure. A control gate (C,G) of each cell is connected to a word line (W/L). A drain (D) of each cell is connected to a bit line (B/L). A source (S) of each cell is connected to a common source line (C,S).
Further, each bit line (B/L) is connected to an input terminal of a sense amplifier (SA). Another input terminal of sense amplifier (SA) is connected to a reference voltage (Vref).
The structure of the general EEPROM cell having the aforementioned circuit construction is shown in FIG. 4. That is, a floating gate (F,G) and a control gate (C,G) are stacked sequentially on a P-type silicon substrate 1. A source region (S) and a drain region (D) formed from N-type impurity regions are formed in P-type silicon substrate 1 on both sides of floating gate (F,G).
An insulating film is formed between silicon substrate 1, floating gate (F,G), and control gate (C,G). Between floating gate (F,G) and control gate (C,G), the insulating film is formed to a thickness corresponding to the thickness of a gate insulating film of a general transistor. Between floating gate (F,G) and silicon substrate 1, a tunnel oxide film is formed to a thickness of about 100 .ANG. or less.
The operation of such general EEPROM is as follows. First of all, in order to write a logic "1" in a cell, 7-8V are applied to bit line (B/L) corresponding to the above cell. A voltage pulse of 12-13V is applied to word line (W/L). The source (S) and substrate 1 are grounded. If so, avalanche breakdown occurs in the P-N junction between drain (D) and substrate 1, thereby generating hot electrons.
A number of the hot electrons generated as described above obtain an energy level higher than the energy potential height (about 3.2 eV) between the substrate and gate oxide film. Then, from the substrate, the electrons travel over the gate oxide film and enter floating gate (F,G), to be stored therein.
At this time, as the number of electrons stored in floating gate (F,G) gradually increases, the threshold voltage of the cell increased. In general, "writing" is performed so that the cell threshold voltage is more than 7V.
If the electrons are stored once in floating gate (F,G), the natural electron discharge quantity is negligibly small because of the energy potential height between floating gate (F,G) and the insulating film fully surrounding floating gate (F,G). Therefore, the quantity of the stored electrons may be maintained without any change, even over the course of several years. Such state of the cell shows a logic "1" in the binary system.
Erasing the data written in the cell described above is as follows. That is, the substrate and control gate (C,G) are grounded. A voltage pulse of 12-13V is applied to common source line (C,S). If so, due to the tunneling phenomenon, the electrons stored in floating gate (F,G) pass the thin gate oxide film from floating gate (F,G) and, then, are discharged to source (S).
At this time, as the discharge quantity of the electrons stored in floating gate (F,G) gradually increases, the threshold voltage of the cell begins to decrease. In general, the cell threshold voltage must be 3V or less. Accordingly, such state shows a logic "0" in the binary system.
The process of reading data stored in the memory cell is as follows. That is, 1-2V are applied to bit line (B/L) connected to drain (D) of the cell. The substrate and source (S) are grounded. Then, a voltage pulse of 3-5V is applied to word line (W/L) connected to control gate (C,G) of the cell.
At this time, in the case where a logic "1" is stored in the cell, the cell enters an "OFF" state, so that the electric charges on bit line (B/L) are not discharged and remain as is. Thus, the previously applied potential of 1V is maintained as is.
In the case where a logic "0" is stored in the cell, the cell enters an "ON" state, so that all electric charges on bit line (B/L) are discharged to source (S) through the cell. Thus, the potential of bit line (B/L) is in a ground state. Sense amplifier (SA) connected to bit line (B/L) recognizes such potential difference of bit line (B/L), thereby reading the stored data of the cell.
In the case of such a general flash EEPROM, it is unnecessary to form the storage capacitor (Cs) required in the DRAM cell, so that the area of the unit cell is decreased. In addition, the process associated therewith is simplified.
However, in the DRAM, the number of times of programming/erasure of data is unlimited. On the other hand, in the EEPROM, the possible times of programming/erasure of data is generally limited to 10.sup.7 or less. Therefore, there is a problem in that the flash EEPROM cannot be used in most applications as a substitute for the DRAM.
This is because, during the programming and erasing of data, a portion of the injected electrons are captured in the gate oxide film when the electrons pass the gate oxide film. Due to the increase of programming/erasure times of data, the captured quantity gradually increases, thereby causing deterioration of the gate oxide film.
If the gate oxide film deteriorates as described above, the speed of programming and erasure is reduced. If the time of programming and erasure is not controlled, the programming threshold voltage is decreased and the erasure threshold voltage is increased, together with the increase of programming/erasure times of data. Accordingly, a so-called "window-closing" phenomenon occurs, such that the device cannot perform the programming/erasure of data after exceeding a predetermined number of times.